1. Field of the Invention
The present invention relates to a structure having integrated thin film transistors, a process for manufacturing the structure, and an electronic device having the structure.
2. Related Art
As a device (as will be widely called the xe2x80x9csemiconductor devicexe2x80x9d) employing thin film transistors (as generally called the xe2x80x9cTFTxe2x80x9d), there are known an active matrix type liquid crystal display device and an active matrix type display device employing EL elements. The thin film transistors have their other applications to a variety of integrated circuits having memory and arithmetic functions.
In recent years, there has been noted an active matrix type liquid crystal display device in which an active matrix circuit (as may also be called the xe2x80x9cpixel circuitxe2x80x9d or xe2x80x9cpixel matrix circuitxe2x80x9d) and a peripheral drive circuit (as may also be called the xe2x80x9cdriver circuitxe2x80x9d) are integrated over a common glass substrate or a quartz substrate. This construction is called the xe2x80x9cperipheral drive circuit integrated type.xe2x80x9d
FIG. 7 shows a summary of a circuit arrangement of a substrate (as will be called the xe2x80x9cTFT substratexe2x80x9d) at the side where the TFTs of the active matrix type liquid crystal display device are formed. Over the common substrate (e.g., a glass substrate or a quartz substrate) 301, as shown in FIG. 7, there are arranged an active matrix circuit 303, and peripheral drive circuits 302 and 304 for driving the active matrix circuit 303. These circuits are composed of the TFTs.
Here, in the peripheral drive circuit 304 (or 302 because both have basically similar structures), as shown at 308 in an enlarged scale, elements 307 including a P-channel type TFT 305 (as will be called the xe2x80x9cPTFTxe2x80x9d) and an N-channel type TFT 306 (as will be called the xe2x80x9cNTFTxe2x80x9d) in combination in the complementary type (or CMOS structure) are arrayed to correspond to the source lines or gate lines of the active matrix circuit.
The numeral 307 designates an analog switch, but a shift register circuit or a buffer circuit is constructed basically of the CMOS elements 307.
The circuit 308 is called the xe2x80x9canalog switchxe2x80x9d, which is located at the final stage for feeding the signal to the source lines finally. In this sense, the circuit 308 is also called the driver circuit or the driver stage.
When the difference in the impedance between wiring lines, it is desired that the CMOS elements 307 are arrayed in a line, as shown in FIG. 7. This array is made to suppress the fine disturbance which might otherwise be caused in the signal to be fed to the active matrix circuit due to the difference in the impedance between the wiring lines.
As a method for forming a crystalline silicon film (as generally expressed as xe2x80x9cP-Sixe2x80x9d) forming the active layer of the TFT, on the other hand, there is a technique making use of a method (as will be called the xe2x80x9claser annealing methodxe2x80x9d) using the irradiation with a laser beam having a linear beam shape.
When this technique is adopted, there is a problem that the crystallization is made slightly different in the dispersion of the energy density in the scanning direction. When a number of elements required to have identical characteristics are to be integrated, therefore, it is preferable that those elements are arrayed in a row, as shown at 308.
The performances, as required of the display device, are a large-area screen, a fine display and a high-speed motion display. The structure, in which the CMOS elements 307 are arrayed in a row, as shown at 308 in FIG. 7, finds it difficult in size and area to meet those requirements.
As a matter of fact, therefore, there is adopted a structure in which the elements are arranged, as shown in FIG. 8. In this structure, more specifically, the numerous elements are staggered from each other.
When this structure is adopted, however, there still remain the aforementioned problems:
(1) the difference in the element characteristics, as caused due to the difference in the crystallization of the active layer between the different stages; and
(2) the difference in the wiring impedance.
These problems cause stripe patterns in the display or unevenness.
Especially the problem (1) involves the stability in the output of the laser annealing apparatus and the errors in the optical system so that its influence cannot be ignored.
The aforementioned problems are mainly caused by the large area (or large size) which is occupied by the CMOS elements 307 of FIG. 7.
If the area, as occupied by the CMOS elements 307, is reduced, therefore, it is possible to array them in a line, as shown in FIG. 7. Then, there arises none of the aforementioned problems.
This problem that the CMOS elements 307 take a large area (or size) will be described in more detail.
FIG. 9 is an enlarged schematic diagram showing a CMOS element 307 of FIG. 7. Reference numeral 214 appearing in FIG. 9 designates a CMOS element having a structure in which the PTFTs and the NTFTs are constructed in the complementary shape. On the other hand, numeral 215 designates a portion of the adjoining CMOS element.
First of all, here will be described the individual parts of the element 214. This element 214 is formed, as its active layer, of a semiconductor layer 202 of the PTFT and a semiconductor layer 216 of the NTFT.
In FIG. 9, numeral 203 designates a gate electrode of the PTFT, and numeral 205 designates a gate electrode of the NTFT. These two gate electrodes are extended and jointed together in a pattern 204.
Numeral 201 designates a source electrode of the PTFT, and numeral 208 designates a source electrode of the NTFT. These two source electrodes are also jointed together in an extended pattern.
Numeral 206 designates a drain electrode shared between the two TFTs. The drain electrode 206 is extended in a pattern 213 to the source line of the active matrix circuit.
Numeral 207 designates openings for contacting with the source region of the active layer 202 of the PTFT. Through these openings, there is established a contact between the source electrode 201 and the source region 202.
When the structure shown in FIG. 9 is adopted, the minimums of the interval between the elements and the size of the elements are determined from the relation in the mask registration accuracy.
Here will be described the case in which the 3 xcexcm rule is adopted for the photolithography, for example.
When the 3 xcexcm rule is adopted, the size, as defined by arrows in FIG. 9, takes 3 xcexcm at the minimum. As a result, the interval between the source contacts of the adjoining elements 217 takes 15 xcexcm at the minimum.
For one CMOS element, moreover, the distance, as designated by 218, takes 9 xcexcm at the minimum.
The present invention contemplates to provide a novel construction which can minimize the area to be shared by elements, when the circuitry shown in FIG. 7 is to be realized, thereby to array the numerous elements in a line.
According to one feature of the present invention, as partially shown of its specific manufacture process in FIG. 5,
when at least two bottom gate type thin film transistors 14 and 15, as arranged adjacent to each other, are to be formed,
the active layer of the two thin film transistors is separated (at an opening 145) in self-alignment by making use of the pattern of source electrodes 138 and 139 (or the pattern of drain electrodes).
According to another feature of the present invention, as partially shown of its specific manufacture process in FIG. 5,
when at least two CMOS elements composed of bottom gate type P- and N-Channel type thin film transistors, as arranged adjacent to each other, are to be formed,
the semiconductor layer forming the two elements is separated (at the opening 145) in self-alignment by making use of the pattern of source electrodes 138 and 139 (or the pattern of drain electrodes).
In the construction shown in FIG. 5, the active layers of the P-channel type thin film transistors (PTFT) and the N-channel type thin film transistor (NTFT), as composing the CMOS element, are formed of a common semiconductor layer.
Another construction of the present invention comprises:
at least two bottom gate type thin film transistors arranged adjacent to each other,
wherein the active layer of the two thin film transistors is separated in self-alignment by making use of the pattern of source or drain electrodes.
Another construction of the present invention comprises:
at least two CMOS elements including bottom gate type P- and N-channel type thin film transistors arranged adjacent to each other,
wherein the semiconductor layer formed the two elements is separated in self-alignment by making use of the pattern of source or drain electrodes.
Adopting these construction described above, a part of the end portions of the elements, as separated at the portions of the opening 145 in FIG. 5, is identical in its side to the end portion of the pattern of the source or drain electrode. This is the result of the self-alignment process making use of the electrode pattern.
These construction can be applied not only to the integrated circuit itself but also to electronic devices using the integrated circuit, such as the display of a data processing terminal or a video camera, as shown in FIG. 18. These devices will be generically called the xe2x80x9celectronic devicexe2x80x9d.